tms320 code engine

The Codec Engine (CE) is a framework which enables several customer use cases, from ARM-side application developers to DSP-side codec authors, and several integrators in between. In many cases, these roles may be played by a single person - in other development environments, a different developer may be assigned each role individually. This topic describes the 4 primary roles which CE users will play, and the inputs and outputs of each role.

Because CE is very portable and configurable, and can run in many different environments, the descriptions of these roles may be intentionally vague. When applicable, specific hardware and software environments are described after the general descriptions.

application using DSP Link on OMAPL1x

application using DSP Link on OMAPL1x

For many developers that have extensive background on TI DSPs, going to an ARM+DSP processor platform usually imposes a difficult learning curve due to the complexity of the interactions between a High Level Operating System (HLOS) and the familiar DSP/BIOS - not to mention the different development environment (usually Linux).

In order to help with such big learning curve, this article covers in detail an example application that not only loads and runs the DSP from the ARM (using the PROC mechanism of DSP/Link) but also allows the DSP to access hardware peripherals directly (either via CSL or BSL). It also shows a safe method of sharing memory (POOL) and passing control messages (Message Queue or MSGQ) between the two operating systems - Linux on the ARM and DSP/BIOS on the DSP.

Updated Release 1.10! Based on feedback received, some fixes and improvements were incorporated to the example application, including a Windows command line version. Please check the differences in the file <readme.txt> on the download page and highlighted in the text below.

FIFO Ordering of DMA Transfers and Linked DMA Transfers

 FIFO Ordering of DMA Transfers and Linked DMA Transfers

Several outstanding DMA transfer requests may be submitted asynchronously to run concurrently on separate logical DMA channels. Only transfer requests started on the same logical channel are guaranteed to start and complete in a strictly first-in first-out (FIFO) ordering.

In order to start multiple DMA transfers simultaneously but in a strict FIFO order, the IDMA3 interface introduces the notion of logical channels with more than 1 configurable transfer. Each ACPY3_start issued on a logical DMA channel, in effect, issues these as linked DMA transfers, similar to the mechanism provided by the EDMA3.0 hardware. In addition to the enforced FIFO ordering, the ACPY3 library submits linked transfers more efficiently, so their use is encouraged even if FIFO ordering is not strictly required.

ACPY3 additionally allows synchronizing with one or more intermediate transfers within a linked channel. The number of intermediate waits must be indicated in the “numWaits” field when requesting an IDMA3 channel that will be used to wait on intermediate transfers.

DMA Transfer Submission and Synchronization using ACPY3

 DMA Transfer Submission and Synchronization using ACPY3

Algorithms or applications can use the physical DMA resources obtained through the IDMA3 interface directly or using any custom DMA library. However, the TI Framework Components package provides a high performance library, ACPY3, which may be used to perform a rich set of DMA operations using the logical DMA channels acquired through the IDMA3 protocol.

The ACPY3 API introduces several DMA transfer-related abstractions highlighted in the following subsections.

TMS320 DMA Resource Management using DMAN3

TMS320 DMA Resource Management using DMAN3

The IDMA3 interface does not specify or mandate the use of a particular framework DMA Resource manager. However, the TI Framework Components package provides DMAN3 as a fully-supported and configurable DMA Resource manager in charge of managing the EDMA3.0 physical resources that the application framework has given exclusively to DMAN3.

In a typical Framework Component based application, DMAN3 grants each algorithm the DMA resources it requests via the IDMA3 interface. The algorithm subsequently may call ACPY3 functions to configure logical channel settings, to request DMA transfers, or to synchronize with on-going transfers.

DMAN3 can be configured using a runtime C interface or statically using XDC tooling. The configuration provides DMAN3 with the physical EDMA3 resources: PaRAMs, TCCs, QDMA channels. DMAN3 configuration dictates how it allocates and manages the memory supplied to each logical DMA channel. DMAN3 additionally supports sharing of physical EDMA3 resources among algorithms created with the same scratch groupId whenever it is possible. It is the responsibility of the application framework to ensure that algorithms created using the same DMAN3 scratch groupIds do not pre-empt each other. See the section titled DMAN3 Configuration Examples for some common allocation scenarios and tips.

TMS320LF2406 Decryption

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Some features of TMS320LF2406 :

1.High-Performance Static CMOS Technology

33-ns Instruction Cycle Time(30 MHz)

30-MIPS Performance

Low-Power 3.3-V Design

2. Based on TMS320C2XX DSP CPU Core

Code-compatible with F243/F241/C242

Instruction Set and Module Compatible With F240/C240

3. On-Chip Memory 

Up to 32K Words x 16 Bits of Flash EEPROM(4 Sectors)

Up to 2.5K Words x 16 Bits of Data/program RAM 

1)544 words of Dual-Access RAM

2)Up to 2k words of Single-Access RAM 

4. Boot ROM 

SCI/SPI Bootloader

5. Two Event-Manager (EV) Modules (EVA and EVB), Each Include:

Two 16-bit general-purpose timers

Eight 16-bit Pulse-width Modulation (PWM)Channels with Enable

1)Three-phase Inverter Control

2)Center or Edge-Alignment of PWM Channels 

decryption parts

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